A throughput maximised parallel architecture for 2D fast Discrete Pascal Transform

In this paper, we present a fully pipelined parallel implementation of a two dimensional (2D) Discrete Pascal Transform (DPT). Our approach rst makes use of the properties of the Kronecker product and the vec operation on matrices to form an alternate 2D DPT representation suitable for column parallel computation. Next, we lend ourselves to the results from Skodras' work in 1D DPT to achieve the nal architecture for fast 2D DPT. With a fully pipelined implementation, the architecture possesses an initial latency of 2(N − 1) clock cycles and a maximum throughput of one complete two dimensional transform every clock cycle, given any input matrix of size N×N . To evaluate our work, our results obtained from actual FPGA implementation were benchmarked against results from other previous works.